A hold fault occurs when there is a delay on the clock path to a capture memory element, and an intermediate memory element launches a transition twice in the time that the capture memory element captures only once. This causes data to move two levels of logic in one clock cycle or at one clock edge.
The classical transition fault model, based on slow-to-rise and slow-to-fall faults, can be used to test setup delay faults on data paths in logic. However, test generation using the classical transition fault model inherently favors setup tests on datapaths. Hold faults on short datapaths are tested only serendipitously. Testing of hold faults on short datapaths is not guaranteed using classical test generation algorithms, e.g., for stuck-at faults or transition faults, which incorporate two clock pulses to launch and capture a test pattern. In particular, the second clock pulse may overwrite the faulty value caused by a hold fault, thus masking such a fault. Accordingly, hold path testing is a difficult problem.
FIG. 1 depicts a simplified circuit 10 that illustrates a situation in which a hold fault may occur. Circuit 10 includes three flip flops 12, labeled A, B, and C for conveying data along a data path 14a, 14b. As shown, there is some amount of delay 18 along the data path 14a between A and B, as well as datapath 14b between B and C. A clock path 16 drives each flip flop 12 (A, B, C), causing data stored in each flip flop to be output after, e.g., a clock transition from low to high. As shown, clock path 16 includes a delay between flip flops B and C that is greater than the delay along the datapath 14b. A hold fault can occur in this case because the data is transferred from A to B before C receives the clock pulse. When C finally receives the clock pulse, C captures the data that A sent to B instead of the data that was residing on B at the time clock pulse was issued.
Testing for hold faults along a short datapath (e.g., B to C) using existing techniques based on slow-to-rise and slow-to-fall faults is not guaranteed. In order to work, the test for the hold fault on the data input of C must ensure that values in the gating side latches allow the test to propagate on the first clock edge or clock pulse. However, existing techniques use two clock pulses to capture to launch and capture the test pattern.
In the presence of a hold fault, data will go from flip flop A to flip flop C in a single clock pulse. Using current techniques, a second clock pulse may overwrite any faulty value in flip flop C, masking the fact that a hold fault occurred.